1. Field of the Invention
The present invention generally relates to the field of image sensors with CMOS active pixels and more particularly to a low-noise CMOS active pixel.
2. Description of Related Art
At present, the main limitation of image sensors with CMOS active pixels lies in the presence of a reset noise in the electrical signals produced by the pixels of the sensor. This reset noise is troublesome because it is preponderant over the other noises in the signal-acquisition analog chain.
A classic CMOS active pixel essentially comprises a photosensitive element, such as a photodiode, associated with three transistors, a selection transistor to select the pixel, a transistor to reset the electrical charge of the photosensitive element and a read transistor to deliver a signal representing the electrical charge of the photodiode before and after the resetting of the pixel. The structure of a CMOS active pixel of this kind is shown in FIG. 1. The photosensitive element, referenced PD, is represented therein by its capacitance CP. A reset transistor MR is connected between a power supply terminal VDD and the photosensitive element. This transistor is connected to the photosensitive element at a point known as a photosensitive node. This photosensitive node is furthermore connected to a gate of the read transistor MD. The drain of the transistor MD is connected to the power supply terminal VDD and its source is connected to the drain of a selection transistor MS. Finally, the drain of the transistor MS is connected to an output terminal S of the pixel. To select this pixel, a signal SEL is applied to the gate of the transistor MS.
A CMOS active pixel of this kind works as follows: during a reset phase (when the RESET signal is active), the potential of the photosensitive element is reset at a fixed value V0. Then, under the effect of a light signal, the electrical charge of the photosensitive element is modified, and the voltage at its terminals then goes from V0 to V0-Vsignal, Vsignal representing the number of incident photons received by the pixel. A method known as the CDS (Correlated Double Sampling) method is then used to read the value Vsignal. In this method, the signal is read at the output of the pixel before and after the resetting of the pixel and then the difference between the two signals is computed to deduce Vsignal therefrom.
This pixel structure has four drawbacks. A first drawback is that the reset phase gives rise to a reset noise in the photosensitive element. This noise is especially high as the capacitance of the photodiode is low. The root-mean-square value of this noise is given by the following formula:
  B  =            kT              C        P            where k is the Boatman constant, T is the absolute temperature and CP is the capacitance of the photodiode. With a capacitance CP of 3 femtofarads, the root-mean-square value of the noise is 1.2 mV at a temperature of 300 Kelvin.
A second drawback is the presence of a power supply noise. Indeed, there is a direct coupling between the voltage power supply source VDD and the photosensitive node by means of the drain-gate capacitance of the read transistor. A power supply noise then gets added to the reset noise in the photodiode.
Furthermore, the use of a MOS transistor as a switch to reset the pixel produces an injection of electrical charges into the photodiode: then, after the MOS transistor has passed into the off state, a part of the electrical charges forming the channel of this transistor is located in the capacitance of the photodiode. The voltage variation that results therefrom is especially high as the capacitance of the photodiode is low. This phenomenon reduces the voltage excursion of the output signal by a fraction that can be relatively big.
Finally, a problem of lag also appears when the reset phase does not succeed in completely erasing the information acquired in the photodiode during the previous reading phase. On a screen, this lag takes the form of a persistence of the image: the image read then contains a residue of the previous image. This problem appears when a small-bandwidth reset technique is used.
To overcome all or a part of these problems, a novel CMOS active pixel structure has been developed. This structure is disclosed in the French patent application filed under number 01/07349, on May 28, 2001 on behalf of the present applicant and the content of which are hereby incorporated hereinto by reference in its entirety. This novel CMOS active pixel structure is illustrated by FIGS. 2 and 3.
With reference to FIG. 2, the CMOS active pixel, referenced P, comprises a photodiode PD with a capacitance CP, an amplifier AMP1 that is active during the reset phase (the signal READ being inactive), a follower amplifier AMP2 active during the read phase (with the signal READ active), two switches IT1 and IT2 series-connected between the output and the inverter input of the amplifier AMP1, and a capacitive element CF having a capacitance CF, parallel-connected with the switch IT1. The photodiode PD is connected between a photosensitive node N and the ground. The non-inverter input of the amplifier AMP1 is connected to an output terminal S of the pixel which receives a reference voltage during the pixel reset phase. The follower amplifier AMP2 which is active during the READ phase is furthermore connected between the photosensitive node and the output terminal S of the pixel.
A more detailed structure of this CMOS active pixel is shown in FIG. 3. A transistor M1 and a row selection transistor M2 are used to form the amplifier AMP1 during the reset phase. These transistors also form the follower amplifier AMP2 during the read phase. Transistors M3 and M4 are also used to form the switches IT1 and IT2.
These components are connected together as follows. The transistor M1 has its gate connected to the photosensitive node N and its source connected to the output terminal S of the pixel. The output terminal S delivers a signal representing the electrical charge of the photodiode during the pixel-reading phase. The selection transistor M2 is cascade-mounted with the transistor M1, namely its source is connected to the drain of the transistor M1. Its drain is connected to a node B common to all the pixels of the column to which the pixel considered is connected and its gate receives a selection signal SEL to select the pixel. The transistor M3, forming the switch IT1, is connected between the photosensitive node N and a point A of the pixel. This transistor is controlled by a reset signal RS1 which is active during a first period φ1 of the pixel reset phase. The pixel reset phase is indeed formed by three consecutive time periods φ1, φ2 and φ3.
The transistor M4 is connected between the node B and the node A. This transistor is controlled by a reset signal RS2 which is active during the time periods φ1 and φ2 of the reset phase. The capacitive element CF is parallel-connected with the transistor M3 between the node A and the node N. Finally, the sum of the capacitive contributions of each pixel of the column of the pixel considered between its respective point B and the ground is shown in the drawing by a capacitor C, connected between the node B and the ground.
The image sensor containing the pixel has means provided to bias and power the pixel during the different phases of operation of the pixel. These means are advantageously common to all the pixels of one and the same column in the image sensor, and even to all the pixels of the image sensor as the case may be. A voltage source VDD and current source SC1 are therefore provided to power the node B of the pixel respectively during the read phase and the reset phase of the pixel. Provision is also made for a second current source SC2 and a voltage source SV having negligible current to impose, respectively, a current during the read phase and a reference voltage VREF during the reset phase on the output terminal S of the pixel.
The working of this CMOS active pixel is illustrated by the timing diagrams of the control signals SEL, RS1, RS2 and READ of FIG. 4. The reading of the information contained in the photodiode after modification of its electrical charge under the effect of a light signal requires a first read phase to acquire a signal representing the illumination of the pixel by the light signal, a phase for resetting the electrical charge of the pixel and a second read phase to acquire a signal representing the initial electrical charge of the pixel. The difference between these two signals gives a signal representing the variation of the electrical charge due to the incident photons of the light signal.
During the first and second phases for reading the pixel, the control signal READ and the selection signal SEL are active while the signals RS1 and RS2 are inactive. In the present case (pertaining to the use of the N channel MOS transistors) a signal is said to be active if it is has a high voltage level and it is said to be inactive if it has a low voltage level.
During the first reading phase, the node B is powered by the power supply voltage VDD and a current is imposed by the current source SC2 on the output terminal S of the pixel. The transistors M3 and M4 are off. The transistor M1, which is then mounted as a follower, is powered through the transistor M2. A voltage signal representing the electrical charge of the photodiode is then available at the output terminal S of the pixel.
Then, during the three periods of the reset phase, φ1, φ2 and φ3, the signal READ is inactive.
During the period φ1 known as the erasure or “hard reset” period, the control signals SEL, RS1 and RS2 are active. The transistors M2, M3 and M4 are therefore conductive. The transistor M1 is mounted as an amplifier and its drain is looped to its gate through the transistor M2.
The pixel is powered by the current coming from the current source SC1 and the reference voltage VREF is imposed on the output terminal S of the pixel. The current given by the current source SC1 goes through the transistors M1 and M2 and is absorbed by the voltage source SV. A potential VREF+VGS(M1) is imposed on the photosensitive node N, with VGS(M1) representing the gate-source voltage of the transistor M1. This period φ1 is used for erasing the information initially contained in the pixel in imposing a fixed voltage at the terminals of the photodiode.
During the period φ2, known as the relaxation period, the control signal RS2 is inactive. The transistor M3 is then off. The noise voltage
      kT          C      F      is sampled on the capacitive element CF. The transistor M1 is in a feedback loop with the capacitive divider formed by the capacitive element CF and the capacitance of the photodiode PD. The transistor M1 then works as an amplifier (amplifier AMP1). Since the transistors M1 and M2 are cascade-connected, a high static gain is obtained for the transistor M1. The gain of the loop formed by the transistors M1 and M2 and the capacitive divider is high despite the capacitive divider. The phase φ2 must be maintained until the amplifier AMP1 reaches a state of equilibrium.
During the period φ3, the control signal RS2 is inactive. The transistor M4 is therefore off. This passage to a low level must be done in a very short time as compared with the time constant of the amplifier AMP1.
This CMOS active pixel structure gives satisfactory results in terms of reset noise, power supply noise, injection of electrical charges into the photodiode and lag as explained very clearly in the French patent application No. 01/07349 cited here above.
However, the gate-drain coupling capacitance of the transistor M3 produces a positive voltage variation at the node B (corresponding to the output of the amplifier AMP1) during the period φ2 of the reset phase. This variation is acceptable so long as the amplifier AMP1 is not saturated and does not clip the signal.
Depending on the etching technology used, this coupling capacitance may be very high. In a borderline case, there is then a very high voltage at the output of the amplifier. This very high voltage is clipped at the value of the power supply voltage VDD minus an unwanted voltage. The progress of the potential at the node B in this case is shown in FIG. 4. Since the output of the amplifier is clipped, it no longer amplifies linearly and the desired effect, i.e. chiefly the correction of the reset noise, is no longer attained.
This coupling actually takes place negatively, during the trailing edge of the control signal RS1. Two phenomena then take place:                the potential at the photosensitive node N drops instantaneously; and        a part of the electrical charges constituting the channel of the transistor M3 is injected into the node N, thus contributing to further lowering the potential of the node N.        
The drop in potential at the node N controlling the gate of the transistor M1 causes the potential at the node B to rise. The lower the capacitance CF, the greater is this rise in the potential at the output of the amplifier. This corresponds to the conditions of making the pixel.
Accordingly, a need exists to overcome the problems of the coupling capacitance of the transistor M3 and to provide an improved CMOS active pixel that is insensitive to this problem.